The Design of a Static CMOS 16 Bit High Speed and Low Power Consumption Hybrid Adder Circuit Using Brent Kung Adder: A Recent Study

Reddy, M. Ramana (2021) The Design of a Static CMOS 16 Bit High Speed and Low Power Consumption Hybrid Adder Circuit Using Brent Kung Adder: A Recent Study. In: New Approaches in Engineering Research Vol. 8. B P International, pp. 101-122. ISBN 978-93-91473-64-8

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Abstract

In this research, a static sixteen Bit CMOS Brent kung adder structure was invented, which boasted a higher speed and reduced power consumption when compared to ripple deliver adders. The speed was improved by altering the shape and adding a Brent Kung adder, which uses (28 transistor, Boolean precise judgement) and is a lot faster than a ripple supply adder. These speed adders will help DSP processors grow. With the use of a 180nm Cadence device, time delays and power consumption are significantly reduced with unique adders.

Item Type: Book Section
Subjects: GO for STM > Engineering
Depositing User: Unnamed user with email support@goforstm.com
Date Deposited: 25 Nov 2023 06:08
Last Modified: 25 Nov 2023 06:08
URI: http://archive.article4submit.com/id/eprint/1908

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